Data-Flow Modelling | Continuous Assignments in Verilog | Vivado 2022.1 | GtkWave | Icarus | EP-4



Published
In this episode we have done Verilog Data-Flow Modeling of a Half-Adder (using Continuous Assignments).
We have also written the Test Bench for Half-Adder using Verilog.
We have simulated the code using Simulators :
Combination-1 : Geany IDE + Icarus Verilog + GTK-Wave
Combination-2 : Vivado 2022.1 ML Edition

_____________Download_URL___________________
halfadder.v : https://bit.ly/3H80Ox1

____________Installation_Guide__________________
Icarus-Verilog & GTK-Wave Installation in Ubuntu 20.04 LTS : https://youtu.be/5MBUrBsH8So
Geany-IDE Installation in Ubuntu 20.04 LTS : https://youtu.be/QOzylhH6Ua0
Vivado 2022.1 ML Edition (Windows-10 & Ubuntu 20.04 LTS ) : https://youtu.be/QoMBkR5Rheg

In this episode we have discussed the below topics :
00:00 Beginning & Intro
00:42 Chapter Index
01:35 Verilog Modelling Methods
02:23 Introduction : Dataflow Modelling
06:29 Continuous Assignments : Dataflow Modelling
12:00 Dataflow Modelling : Half Adder
14:45 Dataflow Modelling : Half Adder Test-Bench
20:43 Code Simulation : Geany IDE + Icarus Verilog + GTK-Wave
24:57 Code Simulation : Vivado 2022.1 ML Edition


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References, Acknowledgements & Credits :
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